1. Field of the Invention
The present invention relates to a semiconductor device such as a vertical MOS field effect transistor (MOSFET) having a trench-type gate and an insulating gate bipolar transistor (IGBT) and its manufacturing method.
2. Description of the Related Art
In view of the high-integration and the low ON-resistance, trench-type vertical MOSFETs have been developed.
A first prior art trench-type vertical MOSFET with a low breakdown voltage such as 20 to 60V includes an n−-type epitaxial layer grown on an n+-type monocrystalline silicon substrate. The n−-type epitaxial layer is formed by an n−-type drain region, a p-type base region and an n+-type source region. Also, a U-shaped trench is formed within the epitaxial layer, and a gate silicon dioxide layer is thermally grown within the U-shaped trench. Further, a gate electrode is buried in the U-shaped trench on the gate silicon dioxide layer (see: FIG. 8 of JP-2002-158355A). This will be explained later in detail.
Since the above-described first prior art trench-type vertical MOSFET has a low breakdown voltage such as 20 to 60V, even when the distance between portions of the p-type base region on the sides of the U-shaped trench, i.e., the width of the trench is small, the ON-resistance of the p-type base region can be sufficiently low. Therefore, in this case, no problem occurs.
In a second prior art trench-type vertical MOSFET with a medium breakdown voltage such as 150 to 250V, the p-type base region is deeper. Therefore, if the width of the U-shaped trench is large, the ON-resistance of the p-type base region is increased. In order to decrease this ON-resistance, the width of the trench is larger (see: FIG. 7 of JP-2002-158355A). This also will be explained later in detail.
In the above-described second prior art trench-type vertical MOSFET, however, the gate electrode is overetched. As a result, since a channel may not be normally generated within the p-type base region, the above-described second prior art trench-type vertical MOSFET would not be normally operated.
In a third prior art trench-type vertical MOSFET, in order to avoid the overetching of the gate electrode, the gate electrode is formed by a double gate, i.e., a first gate electrode, a silicon dioxide layer and a second gate electrode (see: FIG. 1 of JP-2002-158355A). This also will be explained later in detail.
In the above-described third prior art trench-type vertical MOSFET, however, since the gate silicon dioxide layer is so thin to decrease the ON-resistance of the p-type base region and increase the driving ability, the static gate-to-drain capacitance Cgd is increased, which would decrease the switching operation speed.
In a fourth prior art trench-type vertical MOSFET, the gate silicon dioxide layer is modified to be made thicker at the bottom of the U-shaped trench than at the side of the U-shaped trench (see: FIG. 11 of JP-2001-127072A). As a result, the static gate-to-drain capacitance Cgd is decreased to increase the switching operation speed. This also will be explained later in detail.
In the above-described fourth prior art trench-type vertical MOSFET, however, when a gate voltage is applied to the gate electrode, a channel is hardly generated in the p-type base region in the vicinity of the bottom of the U-shaped trench. As a result, the ON-resistance is increased.
In a fifth prior art trench-type vertical MOSFET, in order to effectively generate a channel in the p-type base region in the vicinity of the bottom of the U-shaped trench, a first gate electrode is formed on the side of the U-shaped trench via the gate silicon dioxide layer, and an additional gate silicon dioxide layer is formed at the bottom of the U-shaped trench via the gate silicon dioxide layer. Also, a second gate electrode is formed and is in contact with the first gate electrode and the additional gate silicon dioxide layer. Since the additional gate silicon dioxide layer is added to the gate silicon dioxide layer at the bottom of the U-shaped trench, the static gate-to-drain capacitance Cgd is decreased, which would increase the switching operation speed. Also, since the first gate electrode reaches the bottom of the U-shaped trench, a channel can effectively be generated in the p-type base region in vicinity of the bottom of the U-shaped trench (see: FIG. 1 of JP-11-163342A).